As the integration density of a semiconductor device increases, the importance of low-resistance wiring increases. Currently, a polycide structure wherein refractory metal silicide layers are stacked on a polysilicon layer has been widely used as a low-resistance wiring structure for a bit line, a gate electrode, etc. When the polycide structure is used for a gate electrode, voids may be generated within an interlayer insulating layer formed in a subsequent step due to shrinkage of the silicide material, such as tungsten silicide or titanium silicide, and thus electrical shorts may occur between adjacent landing pads.
Hereinafter, a method for fabricating a conventional polycide gate electrode will be described with reference to FIGS. 1A through 1D. FIG. 1A is a sectional view showing the step of forming a gate pattern comprising a polysilicon layer pattern 20, a silicide layer pattern 25 and a mask oxide layer pattern 30 on a semiconductor substrate 10 on which a gate oxide layer 15 is formed. A low temperature oxide (LTO) is generally used as the mask oxide layer pattern 30.
FIG. 1B is a cross-sectional view showing the gate pattern which is deformed through a cleaning process for removing polymer (not shown) generated on the face of the exposed semiconductor substrate and the surface of the gate pattern during an etching process for forming the gate pattern. At this time, the suicide layer pattern 25 of FIG. 1A is partially removed through the cleansing process resulting in a silicide layer pattern 25a whose right and left sides are recessed.
FIG. 1C is a sectional view showing the step of forming an interlayer insulating layer 35 on the entire surface of the resultant structure on which the cleaning process is performed. Here, the interlayer insulating layer 35 is typically formed of a high-temperature oxide (HTO). During formation of the high-temperature oxide, the silicide material may become crystallized and the volume thereof may shrink. Therefore, the silicide layer pattern 25a of FIG. 1B may become deformed and result in a reduced silicide layer pattern 25b of FIG. 1C. The shrinking of the silicide material may also cause voids 40 to be generated in portions of the interlayer insulating layer 35 extending adjacent to the silicide layer pattern 25b.
FIG. 1D is a sectional view showing the steps of forming a contact hole by a self-aligned contact method using a gate spacer 35a as a mask, and forming a landing pad 45 by filling the contact hole with a conductive material. Here, the gate spacer 35a is formed by anisotropically etching the interlayer insulating layer 35 of FIG. 1C so that a predetermined portion of the semiconductor substrate between adjacent gate electrodes is exposed. Meanwhile, the voids 40 of FIG. 1C are partially etched when the interlayer insulating layer 35 of FIG. 1C is anisotropically etched, thereby forming grooves 40a in the gate spacer 35a. These grooves 40a take the form of elongated grooves along the surface of gate spacer 35a and are typically filled with a conductive material when the conductive material is deposited on the exposed semiconductor substrate 10 to form the landing pad 45.
However, the conductive material filling the grooves 40a may remain even after the landing pad 45 is patterned to expose portions of the filled grooves extending in a third dimension not shown. Thus, parasitic conductive bridges may be formed between adjacent devices. As a result, failure of the semiconductor device may occur.